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3D-IC STCO Physical Design Intern - JR0188139

About the team
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and EDA Eco-System

About the role
- Run Place and Route to design convergence to establish STCO 2D-3D Physical design baseline, assess quality, perform design analysis and 3D PPA optimization
- 3D EDA evaluation and methodology development.
- Inter chiplet analysis and validation with Synopsys 3D-IC Compiler and Cadence 3D Integrity
- Identify design optimization opportunities (silicon, package, EDA, architecture configuration, methodology, etc)
- Analyze architecture critical paths to identify how to best take advantage of this technology
- Identify machine learning opportunities for further optimization

Important behavior trait we look for:
- Highly independent
- Creative
- Out of the box thinker
This is an internship and compensation will be given accordingly based on candidate education level and internship duration.
Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum requirements:

Actively pursuing a MS or PhD degree in Electrical, Computer Engineering or related STEM field.
3+ months experience with the following:
- VLSI Design
- Physical design
- Tools, flow & Methodology (TFM) for STCO/3DIC
- Automated place and route (APR)
- Python, TCL

Preferred:
- Understanding of design methodology and tools features for 2.5D/3D chiplet integration
- Experience with ARM Cores and/or high performance cores.