Digital Design Engineer Intern

SenseICs is looking for engineering students for our 2025 and 2026 INTERNSHIP COHORTS! Students should be expected to work 15-30 hours a week on site at our Columbus, Ohio office.

The digital design engineer intern is expected to have experience/knowledge with circuit design digital flow from Cadence, Synopsys, or other Computer-aided design (CAD) tools and a working knowledge of analog design principles and signal/power integrity. This position is only open for individuals with experience in advanced circuit classes or related work.

Roles and Responsibilities:

1. Writing Verilog/VHDL for ASIC or FPGA
2. Working with Cadence or equivalent Digital ASIC Tool Suite (such as Genus, Innovus, Tempus, Voltus)
3. Working with FPGA design suite (such as Vivado in Xilinx)
4. Working with high-level design, simulation, and verification tools
5. Scripting in Python, PERL, or other high level languages
6. Working of Linux OS and command-line interface

Desired Qualifications:

1. A college degree in electrical engineering, or a related field (Third year or above, graduate level degree is preferred i.e. MSEE or higher)
2. Experience in integrated circuits design, simulation, verification, layout and testing
3. Excellent written communication and presentation skills
4. Ability to communicate complex, technical information to both non-expert and technical audiences
5. Interest working with government contracting
6. Entrepreneurial mindset